High density cavity-up wire bond BGA

ABSTRACT

A new method is provided for mounting high-density wire bond semiconductor devices. A layer of dielectric is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the dielectric layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed. One or more wire bond semiconductor die are inserted into the cavities, are die bonded and wire bonded to the openings that have been created in the layer of dielectric. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.

[0001] This application is related to Attorney Docket #TFM99-002 filedon ______, Ser. No. ______, assigned to a common assignee.

BACKGROUND OF THE INVENTION

[0002] (1) Field of the Invention

[0003] The invention relates to the fabrication of integrated circuitdevices and more particularly, to a novel process and structure formaking packaging substrates for wire bonded semiconductor devices.

[0004] (2) Description of the Prior Art

[0005] When the dimensions of the Integrated Circuits are scaled down,the cost per die is decreased while some aspects of performance areimproved. The metal connections which connect the Integrated Circuit toother circuit or system components become of relative more importanceand have, with further miniaturization of the IC, an increasinglynegative impact on the circuit performance. The parasitic capacitanceand resistance of the metal interconnections increase, which degradesthe chip performance significantly. Of most concern in this respect isthe voltage drop along the power and ground buses and the RC delay ofthe critical signal paths. Attempts to reduce the resistance by usingwider metal lines result in higher capacitance of these wires.

[0006] To solve this problem, the approach has been taken to develop lowresistance metal (such as copper) for the wires while low dielectricmaterials are used in between signal lines.

[0007] Increased Input-Output (I/O) combined with increased demands forhigh performance IC's has led to the development of Flip Chip Packages.Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Alpads on chip and interconnect the bumps directly to the package media,which are usually ceramic or plastic based. The flip-chip is bonded facedown to the package medium through the shortest path. These technologiescan be applied not only to single-chip packaging, but also to higher orintegrated levels of packaging in which the packages are larger and tomore sophisticated substrates that accommodate several chips to formlarger functional units.

[0008] The flip-chip technique, using an area array, has the advantageof achieving the highest density of interconnection to the device and avery low inductance interconnection to the package. However,pre-testability, post-bonding visual inspection, and TCE (ThermalCoefficient of Expansion) matching to avoid solder bump fatigue arestill challenges. In mounting several packages together, such as surfacemounting a ceramic package to a plastic board, the TCE mismatch cancause a large thermal stress on the solder-lead joints that can lead tojoint breakage caused by solder fatigue from temperature cyclingoperations.

[0009] Prior Art substrate packaging uses ceramic and plastic Ball GridArray (BGA) packaging. Ceramic substrate packaging is expensive and hasproven to limit the performance of the overall package. Recent yearshave seen the emergence of plastic substrate BGA packaging; this type ofpackaging has become the mainstream design and is frequently used inhigh volume BGA package fabrication. The plastic substrate BGA packageperforms satisfactorily when used for low-density flip chip IntegratedCircuits (IC's). If the number of pins emanating from the IC is high,that is in excess of 350 pins, or if the number of pins coming from theIC is less than 350 but the required overall package size is small(resulting in a solder ball pitch of less than 1.27 mm.), the plasticBGA structure becomes complicated and expensive. This can be traced tothe multi-layer structure used to create the plastic BGA package. Thismulti-layer structure for the plastic BGA interconnect package isreferred to as the Build Up Multilayer or BUM approach and results in aline density within the package of typically 2-3 mil or 50 u-75 u range.This line density is not sufficiently high for realizing the fan outfrom the chip I/O to the solder balls on the package within a singlelayer. This leads to the multi-layer approach. The multi-layer approachbrings with it the use of relatively thick (50 u-75 u) dielectriclayers, these layers have a TCE (Thermal Coefficient of Expansion) thatis considerably higher than the TCE of the laminate board on which theplastic BGA package is mounted. To counteract this difference in TCE'sthe BUM layers must be (thermally and mechanically) balanced on theother side (the side of the board that does not usually require aninterconnect density provided by the BUM layers) of the laminate board.This latter requirement results in the use of additional material andprocessing steps to apply these materials, increasing the cost of theBGA package and creating a yield detractor.

[0010] Another approach is the use of a flexible film as the startingmaterial. A polymer film, such as the polyimide film or an epoxy basedfilm of 2 to 3 mil thick with or without a copper layer attached to it,is processed by metalization and patterning on one or both sides. Acompleted two metal layer film, described as a layer pair, can be usedas a packaging substrate material. Subsequent dielectric and copperlayers can be build up on the processed first metal layer, such as theRCC (Resin Coated Copper) approach. Alternatively, two or more layerpairs can be bonded together to make a multilayer structure. Theadvantage of this approach is that it uses a minimum amount of material.However, because of the lack of stability of the film, the line andspace density is limited to that of the BUM structure described herein,which is not sufficiently high for the high density packaging that isused to achieve a low cost substrate, having only a few interconnectlayers.

[0011] Other Prior Art applications use thin film interconnect layersfor flip chip or wire bond packaging substrates. These applicationsstart with a laminate substrate onto which the thin film layers aredeposited. For these applications, the laminate substrate is used as abase carrier substrate and provides the mechanical support. PlatedThrough Holes (PTH) are mechanically drilled through the laminatesubstrate and are used to establish connections to the backside of thesubstrate for solder ball attach and electrical contacts. By using thinfilms, high wire density and very thin dielectric layers can berealized. This approach also does not, unlike the BUM approach, requireto counter-balance thick layers of dielectric in order to establishdimensional stability. A disadvantage of the laminate substrate is thatthe process of mechanically drilling holes through the laminatesubstrate is time-consuming thereby adding cost to the process. Further,the planarity of the laminate substrate does not meet planarityrequirements for the deposition of thin films. Good planarity for thesurface of the laminate substrate is established by depositingdielectrics and metal layers on the initial surface of the laminatestructure, steps that again add to the processing cost of the BGAstructure. Since the laminate substrate is composed using organicmaterials, the substrate is not dimensionally stable resulting inwarpage and dimensional variations during high temperature processingand wet chemical interactions. This results in additional processingcomplications and costs.

[0012] The invention teaches a novel process and structure for creatingpackaging substrates that are used for wire bonded semiconductordevices. As such, the process and package of the invention are similarto previous high-density flip chip BGA packages. The term BGA of theinvention refers to the ball grid array that is connected to forinstance a Printed Circuit Board but where the contact balls of thisarray are connected to a (wire bonded) IC device via a substrate that iscreated by the process of the invention.

[0013] U.S. Pat. No. 5,509,553 (Hunter, Jr. et al.) shows a (3) metallayer process (DEMR) (see FIG. 5A) that appears to comprise a) sputterplating base b) plating metal (semi-additive plating), see col. 2.

[0014] U.S. Pat. No. 5,830,563 (Shimoto et al.) discloses a laminatesubstrate with thin films deposited thereon.

[0015] U.S. Pat. No. 5,837,427 (Hwang et al.) shows a (4) BUM processfor a PCB.

[0016] U.S. Pat. No. 5,724,232 (Bhatt et al.) shows a package with a (1)metal substrate.

[0017] U.S. Pat. No. 5,525,834 (Fischer et al.) shows a package having aCu substrate, thin dielectric layers (1-25 um thick) and thin dielectriclayers (12 to 75 um), see col. 7 and 8.

[0018] U.S. Pat. No. 5,877,551 (Tostado et al.) discloses a packagehaving a metal substrate with (2) dielectric layers formed of polymers,epoxy (3 to 100 um), see col. 4.

[0019] U.S. Pat. No. 5,485,038 (Licari et al.) teaches a package using aphoto-imagable epoxy dielectric layer.

SUMMARY OF THE INVENTION

[0020] A principle objective of the invention is to provide aninexpensive and reliable method for high-density wire bond semiconductordevice manufacturing.

[0021] Another objective of the invention is to provide a wire bonddevice package that significantly improves the cooling of the IntegratedCircuit device that is mounted therein.

[0022] Another objective of the invention is to reduce performancelimitations imposed by Prior Art high-density wire bond semiconductormanufacturing techniques.

[0023] Yet another objective of the invention is to provide for high pinfan-out for wire bond semiconductor devices.

[0024] Yet another objective of the invention is to eliminate the needfor counter-balancing the effects of thick layers of dielectric used inconventional high-density wire bond semiconductor device manufacturing.

[0025] Yet another objective of the invention is to provide a method ofpackaging high density wire bond semiconductor devices by using Build UpMultilayer (BUM) technology in combination with thin film depositiontechniques.

[0026] Yet another objective of the invention is to provide an initialsurface with good planarity for the creation of high-density wire bondsemiconductor structures.

[0027] A still further objective of the invention is to provide astructure devoid of warpage and dimensional variations during hightemperature or wet chemical processing for the creation of high-densitywire bond semiconductor structures.

[0028] In accordance with the objectives of the invention a new methodis provided for mounting high-density wire bond semiconductor devices.The invention starts with a metal panel (also referred to as the metalsubstrate); a layer of dielectric is deposited over the first surface ofthe metal panel. One or more thin film interconnect layers are thencreated on top of the dielectric layer. The interconnect layers arepatterned in succession to create metal interconnect patterns. The BUMtechnology allows for the creation of a succession of layers over thethin film layers. Each of the BUM layers created in this manner can becreated for a specific function such as power or ground distribution andsignal or fan-out interconnect. The combined layers of thin film and BUMform the interconnect substrate.

[0029] One or more cavities are created in the second surface of themetal panel; openings through the layer of dielectric are created wherethe wireable metal pad underneath the dielectric is exposed within theperimeter of the cavities. In addition, a metal die pad underneath thedielectric is partially or completely exposed to facilitate die attachand heat removal. One or more semiconductor die are inserted into thesubstrate cavity and are wire bonded to the openings that have beencreated in the layer of dielectric.

[0030] After the fabrication of the metal panel is complete, eachsubstrate on the panel is tested. The substrates are singulated from thepanel by cutting. Openings are created in the bottom BUM layer; solderballs are inserted and attached to this BUM layer for the completion ofthe Ball Grid Array (BGA) package.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1 shows a single chip wire bond chip package with twointerconnect layers.

[0032]FIG. 2 shows the processing steps used during the thin filmdeposition process.

[0033]FIG. 3 shows the processing steps used during the BUM process.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Referring now specifically to FIG. 1, there is shown a crosssection of a single wire bond chip with two interconnect layers.

[0035] The interconnect substrate 12 contains the totality of thesequence of layers that are created within the scope of the inventionfor making a high density packaging substrate.

[0036] The interconnect substrate 12 that has two surfaces. The surfaceof the interconnect substrate into which the contact balls 10 aremounted is the first surface of the interconnect substrate. The surfaceof the interconnect that is in contact with the metal substrate 14 isthe second surface of the interconnect substrate.

[0037] The metal substrate 14 has two surfaces, the first surface 24 ofthe metal substrate 14 is the surface on which the interconnectsubstrate 12 is created. The second surface 26 of the metal substrate isthe surface into which openings are etched for the insertion of wirebond chips.

[0038] The metal layer within the interconnect substrate 12 that isclosest to the first surface 24 of the metal substrate 14 is referred toas the bottom layer, the metal layer within the interconnect substrate12 that is furthest removed from the first surface 24 of the metalsubstrate 14 is referred to as the top layer.

[0039] The two interconnect layers within the interconnect substrate 12are highlighted as 18 (which can be a ground or power layer) and 20(which can be a signal layer). Metal substrate 14, typically copper, isbetween about 30 to 40 mils thick. The metal used for substrate 14 isnot limited to copper but can be other metals such as aluminum orstainless steel.

[0040] The size of the metal substrate 14 is typically 18×24 inches butthe size of the metal substrate 14 is not limited to these dimensions.The process of creating the package of the invention starts with a largemetal panel that contains adequate surface area for the creation of amultiplicity of wire bond packages. This large metal substrate is at agiven point in the process divided into a number of smaller metalsubstrates whereby each of these smaller metal substrates is used tofurther create one package of the invention.

[0041] The invention uses the Build Up Multilayer (BUM) technology (aprinted circuit board technology) in combination with thin filmdeposition technology (a semiconductor like technology used for thecreation of multi chip modules or flat panels).

[0042] It must be noted from FIG. 1 that the metal substrate 14 and thecontact balls 10 are mounted on opposite sites of the interconnectsubstrate 12 while the metal substrate 14 and the contact balls 10 arealso aligned with each other (the metal substrate 14 is located abovethe contact balls 10). It must further be noted from FIG. 1 thatadditional contact balls 11 are provided for connections to theinterconnect substrate 12, these contact balls 11 are located directlyunderneath the wire bond chip 16. The wire bond chip 16 is mounted in anopening 28 that has been created in the metal substrate 14. The opening28 into which the wire bond chip 16 is mounted is a cavity that iscreated by masking and etching of the second side 26 of the metalsubstrate 14.

[0043] A dielectric layer (not shown) is first deposited over the metalsubstrate 14 on the first side 24 of the metal substrate 14. Thisdeposition of the dielectric can be done by either lamination or by acoating and curing process. The layer of dielectric typically has athickness of between about 10 and 50 um. It a required that thedielectric has a TCE (Thermal Coefficient of Expansion) that is higherthan the TCE of the metal substrate. This to assure that, after themetal substrate with the deposited layer of dielectric are cooled downto room temperature, the dielectric film is under tension. Thedielectric layer can be epoxy with or without a thin glassreinforcement, a polyimide film or any other build-up dielectricmaterial.

[0044] The first step in the creation of the interconnect substrate 12is the creation of a thin film interconnect metal layer 20 on top of thelayer of dielectric.

[0045] The thin film deposition technique contains the following steps,see FIG. 2:

[0046]FIG. 2a, depositing an interconnect plating base 50 by consecutivesputtering of Cr, Au and Cr

[0047]FIG. 2b, masking and patterning 52 for semi-additive plating ofthe interconnect pattern;

[0048]FIG. 2c, wet etching the thin Cr layer to expose the Au,depositing semi-additive plating 54 of the interconnect pattern bydepositing Au, Ni and Cu;

[0049]FIG. 2d, removing of the mask 52 (FIG. 2b) for the semi-additiveplating of the interconnect pattern;

[0050]FIG. 2e, wet etching to remove the sputtered plating base 56, FIG.2d, from between the interconnect pattern 54;

[0051]FIG. 2f, coating the created interconnect pattern with a layer 58of dielectric;

[0052] for applications where wire bond connections need to be made tothe interconnect pattern the above dielectric forms a solder mask andvias are created in the dielectric for the solder connections.

[0053] It must be pointed out that, where the example of FIG. 1 showsthe creation of only one layer of thin film, the invention is notlimited to one layer of thin film. A number of thin film layers can besuperimposed, dependent on and determined by design packagingrequirements. Where limitations arise in the number of overlying layersof thin film that can be applied, these limitations are not limitationsthat are imposed by the invention but are rather conventionallimitations of thin film deposition technology or electrical performancecharacteristics.

[0054] The state of the art BUM technology provides the technology toadd layer 18 on top of the created thin film interconnect layer 20, thisadded layer 18 typically can be for power and ground interconnects butcan also be used for fan-out interconnections. Patterns are created inthe additional layer 18, typically for ground and power distribution butnot limited to this.

[0055] It must further be pointed out that, although the example shownin FIG. 1 shows only one BUM layer, the invention is not limited to onlyone such layer. The invention allows for a multiplicity of BUM layersthat can be superimposed over one or more thin film layers.

[0056] It must also be pointed out that the invention does not requirethat a BUM layer is deposited over the thin film layer. It is entirelyconceivable that the package of the invention is created using no BUMlayers and that the interface substrate contains two or more layers ofthin film.

[0057] The last layer created in this manner, that is the layer 18 inFIG. 1 or the layer furthest removed from the first side 24 of the metalsubstrate 14, must provide the interconnects with the contact balls ofthe BGA structure and must therefore be coated as a solder mask.

[0058] The BUM state of the art technology contains the followingprocessing steps, see FIG. 3:

[0059]FIG. 3a, cleaning of the surface of the metal substrate 60 ;

[0060]FIG. 3b, coating of the metal substrate with a dielectric;

[0061]FIG. 3c, creating of vias 64 in the dielectric 62 for electricalconnections to the metal substrate 60;

[0062]FIG. 3d, etching and swelling of the dielectric 66 to roughen thesurface and thereby promote adhesion for the subsequent electrolesscopper deposition;

[0063]FIG. 3d, electroless seeding of the dielectric;

[0064]FIG. 3e, plating of the panel with a layer 68 of copper;

[0065]FIG. 3f, masking and etching the deposited layer of copper tocreate the metal pattern 70 in the BUM layer.

[0066] The second side 26 of the metal substrate must next be preparedfor the mounting of the wire bond chip; an opening or cavity 28 musttherefore be created in the metal substrate 14 that can accommodate thewire bond chip. The second side 26 of the metal substrate 14 istherefore masked and wet etched to create the opening 28 in the metalsubstrate 14. The size of this opening can vary and depends on thenumber of wire bond chips that are to be mounted on the interconnectsubstrate 12. The wet etch of the second side 26 of the metal substrateexposes the dielectric layer that has previously been deposited (on thefirst side 24 of the metal substrate 14, see above).

[0067] It is clear that, although FIG. 1 indicates the mounting of onlyone IC die 16 inside opening 28, the invention is not limited to onedie. By creating a larger opening 28 (or a multiplicity of openings) amultiplicity of IC dies can be inserted into the metal substrate andcan, again using wire bond techniques, be interconnected to theinterface substrate.

[0068] After the cavity 28 has been created in the second surface 26 ofthe metal substrate 14 (thereby exposing the layer of dielectric thathas been deposited over the first surface 24 of the metal substrate),openings are created in the exposed layer of dielectric through whichelectrical contact is established with points of contact in the bottomlayer 20 of the interface substrate 12. One large opening or a matrix ofsmall openings are created in the exposed layer of dielectric on top ofa metal die pad onto which the die is to be placed for the die bondingand heat removal purposes. These openings are created using lasertechnology.

[0069] At this point in the process, the metal panel is subdivided orsingulated into individual metal panels for individual wire bondpackages. Each substrate is electrically tested either before or afterthe metal panel is subdivided into individual substrates.

[0070] Before the wire bond chip is inserted into cavity 28, an adhesivelayer 17 is provided over the surface of the exposed die pad insideopening 28. The wire bond chip 16 is inserted into the cavity 28, thewire bond chip 16 is wire bonded 15 to the bottom layer 20 of theinterconnect substrate. After the wire bond chip 16 has been insertedinto the cavity 28 and the wire bonding has been completed, a glob topor over molding (typically using epoxy) 22 is applied over the wire bondchip 16 thereby providing further protection for the die 16.

[0071] The openings 32 and 33 for the BGA solder ball connections arecreated to expose the top metal pads (the pads in the interconnect layer18 that are furthest away from the metal substrate 14). Interconnectlayer 18 is brought into contact with the contact balls 10 and 11, thecontact balls are attached to layer 18 by reflow of the contact balls.

[0072] It is clear that the packaging of the IC die is at this timecompleted. Electrical contacts have been established by connecting theBall Grid Array solder balls 10/11 (through the interface substrate 12and the wire bond connections 15) to the wire bond pads on the IC die16.

[0073] The invention provides a method for mounting a wire bond IC chipwithin a metal substrate whereby the IC chip is mounted with its activesurface (the surface that contains the points of electrical contact ofthe chip) facing upwards, that is facing away from the above definedinterconnect substrate. It is for this reason that the invention hasbeen designated as a cavity-up (wire bond) package. The chip 16 isconnected to the interconnect substrate 12 using wire bonding 15, asindicated. The chip is further brought into close physical contact withthe underlying interconnect substrate 12 by means of the adhesive layer17 that has been applied between the chip 16 and the interconnectsubstrate 12. The combination of surfaces and substances that surroundthe IC die 16, that is the adhesive layer 17, the (epoxy) glob top/overmolding 22 and the interconnect substrate 12, provide a substantial anddirect path of heat flow from the IC die 16 to the metal substrate 14from where the heat can further be conducted away from the IC die 16through the solder balls 10 and 11 and into the printed circuit boardonto which the package is mounted. Typical thin film dielectric have athickness between about 0.5 and 1.0 mil and are therefore not asignificant inhibitor to heat transfer. Conventional plastic BGApackages use FR4/BT laminates that are several mils thick and havetherefore a high resistance to heat transfer. The invention thereforeprovides a key advantage of significantly improving the cooling the ICdevices that are mounted in the package of the invention.

[0074] Although the invention has been described and illustrated withreference to specific illustrative embodiments thereof, it is notintended that the invention be limited to those illustrativeembodiments. Those skilled in the art will recognize that variations andmodifications can be made without departing from the spirit of theinvention. It is therefore intended to include within the invention allsuch variations and modifications which fall within the scope of theappended claims and equivalents thereof.

What is claimed is:
 1. A method of mounting one or more wire bondIntegrated Circuit chips by creating an interface substrate overlying ametal substrate, comprising the steps of: providing one or more wirebond chips said wire bond chips having been provided with pads for wirebond connections; providing a metal substrate said metal substratehaving a first surface and a second surface; cleaning said first surfaceof said metal substrate; depositing a layer of dielectric over saidfirst surface; depositing a interconnect layer over of said layer ofdielectric thereby forming the first layer of an interconnect substrate;creating a Build Up Multilayer (BUM) layer over said interconnect layerthereby forming the second layer of an interconnect substrate; maskingand etching said second surface of said metal substrate thereby creatingone or more openings for the insertion of said one or more wire bondchips thereby furthermore exposing portions of said dielectric withinsaid openings; selectively creating openings in said exposed dielectricthereby providing electrical access and heat removal to saidinterconnect substrate for said one or more wire bond chips; subdividingsaid metal substrate into individual wire bond substrates; coating saidexposed dielectric of said individual wire bond substrates with a layerof adhesive; inserting said one or more wire bond chips into said one ormore openings for the insertion of said wire bond chips in saidindividual wire bond substrates whereby said wire bond chips overlaysaid adhesive coating; wire bonding said wire bond chips to saidselectively created openings in said dielectric; inserting a moldingcompound over said one or more wire bond chips within said one or moreopenings for the insertion of said wire bond chips; coating said BUMlayer as a solder mask; exposing the metal pads within said BUM layerthereby creating openings for BGA solder connections; and inserting andattaching solder balls to said BGA solder connections.
 2. The method ofclaim 1 wherein said depositing a layer of dielectric over said firstsurface is creating a layer of dielectric with a thickness between about10 and 50 um. and creating vias in the dielectric for electricalconnections between said overlying thin film layer and said wire bond ICchips.
 3. The method of claim 1 wherein said depositing an interconnectlayer is creating a thin film interconnect pattern, comprising the stepsof: depositing an interconnect plating base by consecutive sputtering ofCr, Au and Cr; masking and patterning for semi-additive plating of theinterconnect pattern; etching off the thin Cr to expose the Au layer;depositing semi-additive plating of the interconnect pattern bydepositing Au, Ni and Cu; removing of the mask for the semi-additiveplating of the interconnect pattern; wet etching to remove the sputteredplating base from between the interconnect pattern; coating the createdinterconnect pattern with a dielectric; and creating vias in thedielectric for connections to the overlying layer.
 4. The method ofclaim 1 wherein said depositing an interconnect layer is creating a thinfilm interconnect pattern, comprising the steps of: depositing aninterconnect plating base by consecutive sputtering of Cr/Cu/Cr; maskingand patterning for semi-additive plating of the interconnect pattern;etching off the thin Cr to expose the Cu layer; depositing semi-additiveplating of the interconnect pattern by depositing Cu only; removing ofthe mask for the semi-additive plating of the interconnect pattern; wetetching to remove the sputtered plating base from between theinterconnect pattern; coating the created interconnect pattern with adielectric; creating vias in the dielectric for connections to theoverlying layer; and masking and etching said second surface of themetal substrate thereby creating openings in the dielectric layer; andperforming an additional electroless step or an electrolytic platingstep to deposit Ni and Au on the exposed copper pads thereby ensuring areliable solder connection to the chip.
 5. The method of claim 1 whereinsaid creating a Build Up Multilayer (BUM) layer is: coating saidinterconnect layer with a dielectric layer; etching and swelling saiddielectric layer to promote adhesion to the subsequent electrolessplating of a copper layer; electrolytic plating of the panel surfacewith a layer of copper; masking and etching the deposited layer ofcopper to create the metal pattern in said BUM layer; growing oxide onthe copper surface or micro etching the copper surface thereby promotingadhesion; coating said created metal pattern with a dielectric saidcoating to be applied to the BUM layer as an additional step; andforming a solder mask thereby creating vias in the dielectric forconnections to the BGA solder balls.
 6. The method of claim 1 with theadditional electroless step of depositing a Ni and Au layer on top ofthe exposed copper in the openings for the metal pads within said BUMlayer to ensure a reliable solder connection to the printed circuitboard said additional step to be taken after said creating openings forBGA solder connections.
 7. The method of claim 1 wherein said metalsubstrate contains an element selected from the group of copper oraluminum or stainless steel.
 8. The method of claim 1 wherein said metalsubstrate is a steel panel of the material 400 series said steel panelhaving a Thermal Coefficient of Expansion (TCE) of about 6.1 ppm degreesC.
 9. The method of claim 1 wherein said adhesive layer containsthermally conductive epoxy such as thermoset or thermoplastic epoxy thatcan withstand temperatures of above between about 250 and 300 degrees C.10. The method of claim 1 wherein said metal substrate is less than 40mills thick and has planar dimensions of about 18×24 inches that arelarge enough to provide for one or more individual wire bond metalsubstrates.
 11. The method of claim 1 whereby the Thermal Coefficient ofExpansion of at least one of said dielectrics exceeds the ThermalCoefficient of Expansion of said metal substrate by a measurable amount.12. The method of claim 1 wherein said dielectric contains an elementselected from the group of epoxy with or without thin glassreinforcement or polyimide or a composite dielectric and is deposited toa thickness between about 10 and 40 um using either laminationtechniques or coating and curing techniques.
 13. The method of claim 1wherein said masking and etching said second surface of said metal panelcreates an opening for the insertion of one wire bond chip.
 14. Themethod of claim 1 wherein said masking and etching said second surfaceof said metal substrate creates an opening for the insertion of morethan one wire bond chips.
 15. The method of claim 1 wherein said maskingand etching said second surface of said metal substrate creates one ormore openings for the insertion of one or more wire bond chips.
 16. Themethod of claim 1 wherein said interface substrate contains whenproceeding from the side of the interface substrate that is closest tosaid metal substrate: one or more thin film interconnect layersdeposited over said dielectric layer; a coating of dielectric over thethin film layer that is furthest removed from said metal substrate; anda solder mask thereby creating vias in said coating of dielectric oversaid thin film layer for connections between said thin film layer andthe BGA contact balls.
 17. The method of claim 1 wherein said interfacesubstrate contains when proceeding from the side of the interfacesubstrate that is closest to said metal substrate: one or more thin filminterconnect layers deposited over said dielectric layer; one or moreBUM layers deposited over said second interconnect layer; a coating ofdielectric over the BUM layer that is furthest removed from said metalsubstrate; and a solder mask thereby creating vias in the dielectric forconnections between said BUM layer and the BGA contact balls.
 18. Themethod of claim 1 whereby said claim is extended to include creating amultiplicity of Build Up Multilayer structures and a multiplicity ofthin film interconnect layers said BUM layers overlying said thin filminterconnect layers said thin film interconnect layers to be depositedover said dielectric deposited on said first surface of said metalsubstrate.
 19. A structure for mounting one or more wire bond IntegratedCircuit chips by creating an interface substrate overlying a metalsubstrate, said structure containing: a metal substrate said metalsubstrate having a first surface and a second surface; a layer ofdielectric with a thickness between about 10 and 50 um. deposited oversaid first surface; a thin film interconnect layer deposited over ofsaid layer of dielectric thereby forming the first layer of aninterconnect substrate; a Build Up Multilayer (BUM) layer created oversaid interconnect layer thereby forming the second layer of aninterconnect substrate; one or more openings for the insertion of saidone or more wire bond chips created by masking and etching said secondsurface of said metal substrate thereby furthermore creating exposedportions of said dielectric within said openings; openings selectivelycreated in said exposed dielectric thereby providing electrical accessand heat transfer to said interconnect substrate for said one or morewire bond chips; individual wire bond substrates created by subdividingsaid metal substrate; a layer of adhesive containing thermallyconductive epoxy such as thermoset or thermoplastic epoxy created bycoating said exposed dielectric of said individual wire bond substrates;one or more wire bond chips inserted into said one or more openings forthe insertion of said wire bond chips in said individual wire bondsubstrates whereby said wire bond chips overlay said adhesive coating;wire bonds for said wire bond chips to said selectively created openingsin said dielectric; a molding compound inserted over said one or morewire bond chips and within said one or more openings for the insertionof said wire bond chips; a coating over said BUM layer as a solder mask;the metal pads within said BUM layer created be etching thereby creatingopenings for BGA solder connections; and solder balls inserted andattached to said BGA solder connections.
 20. The structure of claim 19wherein said interface substrate contains when proceeding from the sideof the interface substrate that is closest to said metal substrate: oneor more thin film interconnect layers deposited over said dielectriclayer; a coating of dielectric over the thin film layer that is furthestremoved from said metal substrate; and a solder mask thereby creatingvias in said coating of dielectric over said thin film layer forconnections between said thin film layer and the BGA contact balls. 21.The structure of claim 19 wherein said interface substrate contains whenproceeding from the side of the interface substrate that is closest tosaid metal substrate: one or more thin film interconnect layersdeposited over said dielectric layer; one or more BUM layers depositedover said second interconnect layer; a coating of dielectric over theBUM layer that is furthest removed from said metal substrate; and asolder mask thereby creating vias in the dielectric for connectionsbetween said BUM layer and the BGA contact balls.
 22. The structure ofclaim 19 whereby said claim is extended to include creating amultiplicity of Build Up Multilayer structures and a multiplicity ofthin film interconnect layers said BUM layers overlying said thin filminterconnect layers said thin film interconnect layers to be depositedover said dielectric deposited on said first surface of said metalsubstrate.